In a logic large scale integrated circuit (LSI) after a 65 nm generation, channel mobility of a planar MOSFET is improved by a stress application technique such as a stress liner. However, the stress becomes difficult to apply to the channel with high integration of the LSI. For example, when a gate pitch between planar MOSFETs is small, the narrow gate space between them is closed by the stress liner, so that the stress becomes difficult to apply to the channel. The closure is avoided by thinning the stress liner. However, the stress by the stress liner decreases by the thinning, so that a sufficient stress cannot be applied to the channel.
On the other hand, a fin FET attracts attention as a transistor which is stronger against a short channel effect than the planar MOSFET, and is therefore advantageous for miniaturization. However, it is known that channel mobility of the fin FET is degraded by miniaturizing the fin width. Therefore, introduction of a mobility improvement technique is required for the fin FET. It is reported that the stress application technique which is effective to the planar MOSFET is also effective to the fin FET. However, the application of the stress to the channel of the fin FET becomes difficult with high integration of the LSI, similarly to the planar MOSFET. Therefore, the stress application technique is required which can improve the channel mobility of the fin FET even if the LSI is highly integrated.